6A, 1kV 4H-SiC Normally-off Trenched-and-Implanted Vertical JFETs

This paper presents the design, fabrication and characterization of 4H-SiC trenched-andimplanted vertical JFETs (TI-VJFETs) [1]. The design of TI-VJFETs with active areas of 9.38×10 -2 mm 2 and 2.03mm 2 and different vertical channel openings is presented based on a blocking layer of 9.4μm, doped to n=7x10 15 cm -3 . Highly vertical channel defined by trench etching and angled implantation of Al makes it possible to accurately control the vertical channel dimension, resulting in TI-VJFETs with very low specific on-resistance. The TI-VJFET technology developed under this work is believed to be advantageous in comparison to other reported VJFET technologies because (a) it eliminates the need for epitaxial regrowth in middle of the device fabrication [2-5], (b) only one mask requires critical alignment throughout device fabrication, and (c) it provides intrinsically a much lower specific on-resistance due to the elimination of internal lateral JFET gates. Successful applications of the technologies to the development of single-cell TI-VJFETs with power level of 6A -1,000V are reported. Introduction SiC is an excellent semiconductor for high power and high temperature applications. Among the power switches being actively pursued, vertical JFET is especially attractive because it is free of gate oxide related problems. Most of the past demonstrations of JFETs [2,3] are normally-on except for a vertical JFET demonstrated with internal lateral JFET gates [4,5] which requires an epitaxial re-growth that adds an extra on-resistance resulting from the lateral JFET channel. This paper presents the design and fabrication by an advanced self-aligned technology of a trenched and implanted VJFET, which overcomes the existing problems of the SiC VJFETs. Fig.1. Cross sectional view of TI-VJFET. Materials Science Forum Vols. 457-460 (2004) pp. 1213-1216 online at http://www.scientific.net © (2004) Trans Tech Publications, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of the publisher: Trans Tech Publications Ltd, Switzerland, www.ttp.net. (ID: 204.52.215.2-21/02/07,16:17:10) Device Design The cross sectional view of the TI-VJFET is shown in Fig.1. The design target is to develop TI-VJFETs suitable for power inverter applications with bus voltages up to 600V. The design of the TI-VJFETs involves optimization of a set of critical parameters including the vertical channel opening, vertical channel doping concentration, gate formation and implantation condition, and trench mesa width and depth. The vertical channel region and the drift layer are both implemented by a single n layer doped to 7×10 15 cm -3 . The blocking layer, the n drift layer between the p + body and the n + substrate, is designed to have a thickness of 9.4μm taken into consideration of Al implantation tail, which yields a theoretical breakdown voltage of 1,741V. The device active area is either large (2.03×10 -2 cm 2 ) or small (9.38×10 -4 ) cm 2 . The widths of the mesa and vertical channel opening are designed, based on a large number of computer simulations, to have dimensions in the range of 1.45 to 1.95μm and 0.55 to 0.95μm, respectively. Self-aligned Processing and Device Fabrication The device fabrication starts with the etching of the deep trenches by inductively-coupled plasma (ICP) using CF2 and O2 gas mixture, forming the source mesa arrays shown in Fig.2(a). Because of the presence of the deeptrenched structures, self-aligned processes become possible based on planarizing coating of photoresist (Fig.2(b)) and etching-back by oxygen plasma to expose the mesa tops (Fig.2(c)) for blank metal sputtering (Fig.2(d)) and the subsequent self-aligned metal mask formation by lift-off (Fig.2(e)). The implementation of p+ gate by multi-step implantation becomes greatly simplified by the use of self-aligned implantation mask placed on the mesa top. Once the implantation metal mask is formed on the mesa top, the sample is subjected to Al implantation to form the gate structure shown in Fig.1, followed by removing implantation mask and post-implantation annealing at 1,550°C for 30min. The sample is then dry-etched to form a two-step JTE by ICP etching [6] plus surface passivation by a 50nm thick thermal oxide grown at 1,100°C for 30min in wet O2 followed by a 200nm thick PECVD silicon nitride. After the edge termination structure is formed, passivation dielectric is removed from only the mesa tops and the source Ni contacts are defined by using the same selfaligned processes described in Fig.2 and the result is presented in Fig.3. Annealing of source Ni is done at 1,050°C for 10min with the drain Ni/Al (300/20nm) Fig.2. Self-aligned processes Fig.3. Microphoto showing formation of source ohmic contact by selfalignment after device passivation. Fig.4. Microphoto showing top view of the fabricated large and small TIVJFETs. Silicon Carbide and Related Materials 2003 1214